Research

Machine Learning for EDA

As the technology node of integrated circuits rapidly scales down to 5nm and beyond, the electronic design automation (EDA) in Very Large Scale Integration (VLSI) which has been developed over the last few decades, is challenged by the ever-increasing VLSI design complexity. Machine learning has shown great potential in various fields, including EDA. Our major achievements are proposing and customizing machine learning techniques in many EDA applications. Our research topics include design optimization, performance modeling, and co-optimization. Selected publications:

  • Donger Luo*, Qi Sun*, Xinheng Li, Chen Bai, Bei Yu, Hao Geng, “Knowing The Spec to Explore The Design via Transformed Bayesian Optimization”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.

  • Yibo Qiao, Weiping Xie, Shunyuan Lou, Qian Jin, Lichao Zeng, Yining Chen#, Qi Sun#, Cheng Zhuo#, “Minimizing Labeling, Maximizing Performance: A Novel Approach to Nanoscale Scanning Electron Microscope (SEM) Defect Segmentation”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.

  • Hongquan He, Guowen Kuang, Qi Sun, Hao Geng, “Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern Recognition”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25-27, 2024.

  • Donger Luo, Qi Sun, Qi Xu, Tinghuan Chen, Hao Geng, “Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25-27, 2024.

  • Tinghuan Chen, Hao Geng, Qi Sun, Sanping Wan, Yongsheng Sun, Huatao Yu, Bei Yu, “Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization”, accepted by ACM Transactions on Design Automation of Electronic Systems (TODAES).

  • Chen Bai, Qi Sun#, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D.F. Wong, “BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 29, no. 01, pp. 1–23, 2024.

  • Guojin Chen, Wanli Chen, Qi Sun, Yuzhe Ma, Haoyu Yang, Bei Yu, “DAMO: Deep Agile Mask Optimization for Full Chip Scale”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 9, pp. 3118-3131, Sept. 2022.

  • Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, Bei Yu, “Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 27, no. 4, 2022.

  • Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu, “Deep H-GCN: Fast Analog IC Aging-induced Degradation Estimation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 7, pp. 1990-2003, 2022.

  • Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu, “Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Jan. 18–21, 2021.

  • Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D.F. Wong, “BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 1–4, 2021. (William J. McCalla Best Paper Award)

  • Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu, “Global Placement with Deep Learning-Enabled Explicit Routability Optimization”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Feb. 01–05, 2021.

  • Qi Sun, Tinghuan Chen, Siting Liu, Jin Miao, Jianli Chen, Hao Yu, Bei Yu, “Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Feb. 01–05, 2021. (Best Paper Award Nomination)

Deep Learning Inference Acceleration

Deep learning has achieved significant success in a variety of real-world applications. However, most of the existing deep learning models are still by manual design, and how to achieve an automatic and efficient model design is still an open problem. To address this problem, our major achievements are proposing hardware-friendly deep learning models and deployment optimization techniques. Selected publications:

  • Yuxuan Zhao, Qi Sun#, Zhuolun He, Yang Bai, Bei Yu, “AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution”, AAAI Conference on Artificial Intelligence (AAAI), Feb. 7–14, 2023.

  • Wenqian Zhao, Yang Bai, Qi Sun, Wenbo Li, Haisheng Zheng, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Martin D.F. Wong, “A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

  • Qi Sun, Xinyun Zhang, Hao Geng, Yuxuan Zhao, Yang Bai, Haisheng Zheng, Bei Yu, “GTuner: Tuning DNN Computations on GPU via Graph Attention Network”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10–14, 2022.

  • Qi Sun, Chen Bai, Tinghuan Chen, Hao Geng, Xinyun Zhang, Yang Bai, Bei Yu, “Fast and Efficient DNN Deployment via Deep Gaussian Transfer Learning”, IEEE International Conference on Computer Vision (ICCV), Oct. 11-17, 2021.

  • Wenqian Zhao, Qi Sun, Yang Bai, Haisheng Zheng, Wenbo Li, Bei Yu, Martin D.F. Wong, “A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 1–4, 2021.

  • Qi Sun, Chen Bai, Hao Geng, Bei Yu, “Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Feb. 01–05, 2021.

  • Qi Sun, Tinghuan Chen, Jin Miao, Bei Yu, “Power-Driven DNN Dataflow Optimization on FPGA”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4–7, 2019.